Logic circuit

Abstract

A logic circuit, most suitable for the NOR gate, logic function and integration on a single chip with a plurality of such logic circuits and other digital circuits receiving the outputs of the logic circuits and the logic circuits themselves connected and cascade, wherein plural groups of input transistors are provided, with a load through the voltage source and one of the groups, field effect transistor between the voltage source and the other group, so that its gate is connected to the node between the load and first group and its source is connected to the output terminal, with the improvement being in finding a leakage load for the field effect transistor through the voltage source, providing a clamping circuit for the gate of the transistor. The clamping circuit can include a transistor having its gate connected to the output with a delay so that it will not come on until after a substantial portion of the rise time of the output has expired. An additional logic output may be taken from the gate of this transistor, preferably through a transistor to match the outputs, so that the logic circuit is provided with two independent outputs useful for providing adjacent logic or digital circuits with a conveniently close terminal for input, and further to take advantage of the isolation of the outputs by providing other directions for both outputs for circuit elements that must remain isolated, for example in cross coupling two logic circuits as a flipflop. One or more of the may be a field effect transistor, particularly provided with boot strapping. For otherwise identical logic circuits as a part of an overall integrated logic circuit, the clamping circuits may differ only with respect to matching respective output voltages or respective output currents with respective fan outs or other characteristics of load circuits to be driven by the outputs. Preferably, all of the elements are constructed of field effect transistors.