Reconfigurable signal processor

Abstract

An interconnection scheme among the processing elements ('PEs') of a multiprocessor computing architecture realizes, through PE reconfiguration, both fault tolerance and a wide variety of different processing topologies including binary trees and linear systolic arrays. By using a novel variant on a tree expansion scheme, the invention also allows for arbitrary up-sizing of the PE count to build virtually any size of tree network, with each size exhibiting same high degree of fault tolerance and reconfigurability. The invention may be practiced with 4-port PEs arrayed in a module comprising a 4.times.4 board-mounted PE lattice. Each PE has four physical ports, which connect to the similar ports of its lattice neighbors. Each PE has an internal capability to be configured to route signals to or from any of its neighbors. Thus, for tree topologies, any of the four neighbors of a given PE may be selected as the parent of the given PE; and any or all of the remaining three neighboring PEs may be selected as the child(ren) PEs. The PE ports are configured under the control of a remote host, which establishes an initial desired PE topology. The operability of the PEs is tested, and information on faulty PEs or communications paths is used to enable or disable nodes as necessary by revising the PE port configurations. The nodes thus are reorganized and can run or continue running, on a degraded basis.