Single package, multiple, electrically isolated power semiconductor

Abstract

Single package, electrically isolated dual, triple, quad, etc., power semiconductor devices are provided without use of ceramic or other isolators between the semiconductor die and the die support. For example, isolated dual power transistors, each having three leads, are encapsulated within the same package outline and lead footprint as a seven lead TO-218 or TO-220 by dividing the die flag into two spaced-apart portions, one for each die, connecting the first three leads to the first transistor and die flag, connecting the last three leads to the second transistor and die flag, and omitting the centrally located fourth lead. The spaced-apart die flags and leads are supported by a molded encapsulation.