The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 1991

Filed:

Apr. 20, 1990
Applicant:
Inventors:

Alan W Kleinsasser, Putnam Valley, NY (US);

Jerry M Woodall, Bedford, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437175 ; 437176 ; 437177 ; 437178 ; 437179 ; 357-6 ; 357-7 ; 357 15 ; 148D / ; 148D / ; 148D / ;
Abstract

A method and structures are described for fabricating junctions having metal electrodes separated by polycrystalline barriers with arbitrarily-chosen but controlled barrier height and shape is accomplished by varying the composition and doping of polycrystalline multinary compound semiconductor materials in the barrier, hence varying the Fermi level pinning position such that the Fermi level is fixed and controlled at and everywhere in between the two metal-insulator interfaces. It is known that Schottky barrier heights at metal/compound semiconductor interfaces are determined by a Fermi level pinning mechanism rather than by the electronic properties of the applied metallurgy. The present invention exploits the knowledge that the same type of Fermi level pinning occurs at semiconductor dislocations and grain boundaries. The present invention uses polycrystalline compound semiconductor alloys in which the pinning position is varied over a large range in metal/semiconductor structures. The structures are composed of sandwiches of metal, compound semiconductor and metal. Tunneling currents are determined by barrier height, controlled by semiconductor alloy composition, and semiconductor thickness. The energy barrier in the polycrystalline material can be uniform throughout, due to the uniformity of pinning position at both the metal/semiconductor interface and the grain boundaries.


Find Patent Forward Citations

Loading…