The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 1991
Filed:
Oct. 19, 1989
Masanobu Yoshida, Yokohama, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A semiconductor memory device has a decoder circuit. The decoder circuit includes a load transistor T.sub.1, a NAND gate circuit, i.e., a driver circuit serially connected to the load transistor T.sub.1 and includes a plurality of driving transistors T.sub.2 to T.sub.5 serially connected each other. An inverter IV is connected to the node N.sub.1 formed between the load transistor T.sub.1 and the NAND gate circuit. An additional load current increasing device T.sub.8 is connected to the node N.sub.1 or to a contact portion formed between two transistors arranged adjacently to each other in the NAND gate circuit. The load current increasing device T.sub.8 is operable only in the reading mode for increasing the load current and thus to increase the threshold voltage level of the decoder circuit up to about V.sub.cc /2, thereby preventing erroneous operation of the decoder and the memory cell array.