The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 1991
Filed:
Jun. 16, 1989
Tamas S Szepesi, San Jose, CA (US);
National Semiconductor Corp., Santa Clara, CA (US);
Abstract
A current limiting circuit (200, 300, 400) for instantaneously limiting the peak current of a fast high side power switch (212) or power FET has a reference switch (213) or FET, a first comparator (218), a current source I.sub.CL, control circuitry (209), and a clamping circuit (238). The reference FET (213) is smaller than the power FET (212). The first comparator compares the voltage drop across the power FET (212) and compares it with the voltage drop across the reference FET (213) and produces a signal COMPOUT which initiates the turn-off of the power FET (212) if the voltage drop across the power FET (212), caused by a load current flowing through it, is greater than or equal to the reference FET voltage drop induced by I.sub.CL. The clamp circuit (238), having diodes (D.sub.1, D.sub.2) and a tracking current source I'.sub.CL, disconnects the FETS (212, 213) from the comparator (218) when they are OFF. The circuit (200, 300, 400) may also have a second comparator (250) which protects the power switch (212) from a short circuit condition in the circuit (200, 300, 400).