The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 1991

Filed:

Nov. 30, 1989
Applicant:
Inventor:

Naomasa Sugita, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
A01L / ;
U.S. Cl.
CPC ...
357 15 ; 357 52 ; 357 58 ; 357 22 ;
Abstract

A semiconductor device comprising a semiconductor substrate having two major surfaces a cathode electrode film formed on the first major surface of the substrate, and an anode electrode film formed on the second major surface of the substrate. The substrate is formed of an N.sup.+ -type layer formed on the cathode electrode film, an N.sup.- -type layer formed on the N.sup.+ -type layer, and N.sup.-- -type layer formed on the N.sup.- -type layer and having an impurity concentration lower than that of the N.sup.- -type layer, and an N.sup.- -type layer interposed between the N.sup.-- -type layer and the anode electrode film. The device further comprises a plurality of P.sup.+ -type areas formed in the second major surface of the substrate, contacting the anode electrode film and extending through the N.sup.- -type layer and the N.sup.-- -type layer into the N.sup.- -type layer. When a forward bias is applied to the device, a current flows from the anode electrode film, passes through the N.sup.- -, N.sup.-- -, N.sup.- - and the N.sup.+ -type layers, and flows out of the cathode electrode film. When a reverse bias is applied to the device, the depletion layer formed around the junction between each P.sup.+ -type area and the N.sup.-- -type layer extends, and joins with the similar depletion layers, thereby pinching off the current path. As a result, the reverse leakage current is reduced.


Find Patent Forward Citations

Sugita, Naomasa. (1991). Semiconductor device having intermediate layer for pinching off (U.S. Patent No. 5017976). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5017976

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…