High-speed modified successive approximation analog to digital converter

Abstract

A high-speed algorithmic successive approximation analog to digital converter includes a system input terminal, and a tri-state comparator having an input terminal connected to the signal sampler. The comparator produces a first indication of a signal on its input terminal exceeds an upper reference voltage and the comparator produces a second indication if a signal on its input terminal exceeds the lower reference voltage, and does not exceed the upper reference voltage. A subtractor is connected to the system input terminal and to the comparator for subtracting from a received signal a first value corresponding to the upper reference voltage if the comparator produces the first indication, or a second value corresponding to the lower reference voltage if the comparator produces the second indication. The system additionally includes a multiplier having an input terminal connected to the output of the subtractor for doubling the output of the subtractor for further processing by the same or similar comparator assemblies. The comparator preferably includes first and second comparators, each for comparing the signal input with one of the upper and lower reference voltages, and logic connected to the output terminals of the comparators for producing the second indication only if the first indication is not produced.