Method and circuit for eliminating major bit transition error at the

Abstract

A digital-to-analog converter converts a digital word of M+N bits to an analog signal with reduced bit switching error, by providing a first group of M input conductors conducting the M most significant bits of the digital word, a second group of N input conductors conducting the N least significant bits of the digital word, and an M bit plus 1 adder having M inputs connected to a corresponding conductor of the first group. A signal representative of the most significant bit of the digital input word is coupled to an input of the adder. The adder has M output conductors. Signals on the N input conductors of the second group together with signals on the M output conductors from an intermediate digital word of M+N bits differ in value from the first digital word. An M+N bit DAC receives the intermediate digital word and produces an analog current corresponding to the value of the intermediate digital word. A switched current source responsive to the most significant bit of the digital input word produces an offset current and algebraically sums it with the analog current to produce an analog output current. The offset current has a value equal in magnitude and opposite in polarity to the shift in the analog current produced by the coupling of the most significant bit of the digital input word to the input of the adder such that the analog output current corresponds to the value of the first digital word.