The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 1991

Filed:

Feb. 26, 1990
Applicant:
Inventor:

Dhaval J Brahmbhatt, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365185 ; 365181 ; 36518908 ; 307465 ;
Abstract

An Electrically Programmable Read Only Memory (EPROM) memory cell includes a serially connected Complementary Metal Oxide Silicon (CMOS) transistor pair having common floating gates and common control gates. A third n-type floating gate field effect transistor is utilized for programming the memory cell. The floating gate and the control gate of the third transistor are connected to the common floating gates and the common control gates, respectively, of the Complementary Metal Oxide Silicon (CMOS) transistor pair. The memory cell is tri-statable by connecting the source of the p-channel transistor of the Complementary Metal Oxide Silicon (CMOS) pair to the common control gates.


Find Patent Forward Citations

Brahmbhatt, Dhaval. (1991). Logic cell array using cmos eprom cells having reduced chip surface area (U.S. Patent No. 5016217). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5016217

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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