The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 1991
Filed:
Dec. 01, 1989
Grady L Giles, Austin, TX (US);
Jesse R Wilson, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A toggle-free scan flip-flop (TFSFF) is provided which is designed for use during a test mode scan operation. The toggle-free scan flip-flop has the capability of not toggling its parallel output during test mode scan operation. The TFSFF uses a master latch, which is controlled by a scan multiplexor, to selectively update two alternate slave latches. Switching logic controls the determination of which alternate slave latch is updated with the incoming data signal. An existent scan enable (SE) signal controls the switching logic, and thus, the TFSFF design requires no additional control signals for its operation. During the scan test mode, the data is clocked through the TFSFF from a Scan-Data-In terminal, and out the Scan-Data-Out terminal, without affecting the system data output Q. The shift sequence is followed by a capture interval, during which the Q output is automatically updated with the desired data to test the target logic. Thus, the logic under test is not affected by the loading of the scan test vector, since the parallel system output Q of the TFSFF does not toggle during the shifting sequence.