The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 1991

Filed:

Sep. 25, 1990
Applicant:
Inventor:

Robertus D Verhaar, Eindhoven, NL;

Assignee:

U.S. Philips Corporation, Tarrytown, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 44 ; 437 41 ; 437233 ; 437191 ; 357 233 ; 156643 ;
Abstract

Method is set forth of manufacturing a device comprising MIS transistors having a projecting gate on the weakly doped parts of source and drain regions. A method comprising the deposition of a first and a second polycrystalline conducting layer, which are separated by an insulating layer. According to the invention, gate islands (20) are formed in the second polycrystalline layer (14) and the ion implantation of the weakly doped portions (21, 22) of the source and drain zones is effected through the assembly of the insulating layer (13) and the first polycrystalline layer (12). A third polycrystalline layer (23) is then deposited, which layer contacts both the island of the second polycrystalline layer (14) and the first polycrystalline layer (12). Widened gate islands (26) are finally marked off by means of the insulating spacer technique (25), in which islands there remain only present the portions (23') of the third polycrystalline layer (23) in the shape of an 'L'. The highly doped portions (28, 29) of the source and drain zones are then implanted.


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