The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 1991
Filed:
Aug. 25, 1989
Kaneyasu Shimoda, Kawasaki, JP;
Yuzo Ageno, Yokohama, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A sequential decoder for decoding a systematic and convolutional code signal having a code rate greater than 1/2 and carrying out error correction coding of the code signal. A local most likely path in a plurality of possible paths for a newly received information bit is determined by calculating a branch metric indicating likelihood of each of the plurality of possible paths in accordance with a predetermined algorithm. The path decision is carried out by a construction including a two-path comparing path decision circuit which receives a pair of bits comprised of an information bit and a parity bit at one time and determining a local most likely path between two possible paths for the information bit. A four-path comparing path decision circuit receives a pair of information bits at one time and determines a local most likely path among four possible paths for the pair of information bits. A parity bit timing detecting circuit detects a timing of an input of the above pair of bits comprised of an information bit and a parity bit. A selecting circuit selects an output of the above two-path comparing path decision circuit at the input timing of the above pair of bits comprised of an information bit and a parity bit, and selects an output of the above four-path comparing path decision circuit at the timing of the input of the above pair of information bits.