Device for synchronizing a pseudo-binary signal with a regenerated clock

Abstract

A synchronizing device synchronizes a pseudo-binary signal particularly affected by high jitter with a regenerated clock signal into a synchronized signal. The device can be included between an output of a bipolar-to-binary converter receiving a plesiochronous bipolar signal and an input of a HDB/binary transcoder in a synchronizing circuit of a time-division multiplexer. The clock signal has a period Tj substantially lower than the nominal period of the pseudo-binary signal and offers phase jumps, particularly included between Tj/2 and Tj, for the clock signal to have a mean period equal to the nominal period. The device preferably comprises, on the input side, a flip-flop used as a divide-by-2 frequency divider for providing a first logic signal alternately having logic levels '0' and '1' in response to transitions '0' to '1' in the pseudo-binary signal, then a second flip-flop for phasing the transitions in the first logic signal with active transitions '0' to '1' of the clock signal thereby deriving a phased logic signal, and two flips-flops and a Exclusive-OR gate for supplying the synchronized signal with pulses which are at level '1' and which have a width calibrated as a function of the period of the clock signal and which are respectively derived in response to the transitions of the phased signal.