Single ended sense amplifier with improved data recall for variable bit

Abstract

A single ended sense amplifier senses whether or not a memory cell in an array conducts current from a bit line conductor to which the sense amplifier is connected. A first stage of the sense amplifier includes a number of separately biased transistors which establish a lower voltage level at a node when the cell conducts current than the higher voltage level at the node when the cell does not conduct current. A second stage of the sensed amplifier includes transistors connected in an inverting arrangement to receive the signal from the node and supply an output signal at an output terminal in response thereto. An equalizing transistor is selectively connected between the node and the output terminal and establishes a high gain bias point voltage at the node when conductive. The high gain bias point in intermediate the higher and lower voltages established at the node by the first stage. As soon as the equalizing transistor becomes nonconductive, the second stage is immediately driven to the correct output signal level by the voltage at the node from the first stage. A precharge transistor is conneced to the bit line to raise the voltage on it to a predetermined high level, thereafter allowing the voltage to decay before sensing the logical state of the cell. Precharging the bit line avoids the uncertainties associated with charging the bit line capacitance.