The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 1991

Filed:

Jan. 23, 1989
Applicant:
Inventors:

Pierre M Petroff, Santa Barbara, CA (US);

Herbert Kroemer, Santa Barbara, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437110 ; 148D / ; 148D / ; 148D / ; 148D / ; 156610 ; 437107 ; 437133 ; 437936 ;
Abstract

A method for growing a superlattice structure on a substrate. First, a periodic array of monoatomic surface steps are created on the surface of the substrate at an area to have the superlattice structure grown thereon. There is apparatus for creating a beam of a material being input thereto and for selectively including or not including respective ones of a plurality of materials within the beam. The beam is directed at the steps of the substrate. Finally, logic causes control apparatus to include and not include respective ones of the materials within the beam in a pre-established pattern of time periods which will cause the materials to be deposited on the steps in a series of stacked monolayers. Tilted Superlattices (TSLs) and Coherent Tilted Superlattices (CTSLs) are created. The method can create pseudo ternary semiconductor alloys as part of a CTSL by employing at least two binary compound semiconductor alloys in the deposition process. It can also create a quantum wire superlattice by sandwiching a thin CTSL layer between two wider band gap layers. Additionally, it can create a tilted superlattice with zero misfit strain by using three binary compounds to produce a pseudo-ternary compound in a direction parallel to the substrate normal while the tilted superlattice structure provides a desired band gap in a direction parallel to the substrate surface. One may form the CTSL as part of a field effect transistor (FET) wherein the CTSL is part of the FET gate or form the CTSL as the cladding layers of a quantum wire laser having a GaAs active layer.


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