The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 1991

Filed:

Nov. 03, 1989
Applicant:
Inventor:

Hugh W Littlebury, Chandler, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ; G01R / ;
U.S. Cl.
CPC ...
3241 / ; 324 725 ; 3241 / ;
Abstract

A method of testing unpackaged integrated circuits using a tester which is capable of testing a plurality of memories in parallel is provided. A membrane test head having a plurality of probe bumps thereon is provided wherein the probe bumps are coupled to the tester by microstrip transmission lines formed on the membrane test head. The semiconductor memory has a plurality of contact pads thereon which are coupled to the probes. In this manner, a plurality of semiconductor memories can be tested in wafer form. Alternatively, individual semiconductor memory chips can be mounted on a receiver plate and tested individually or in parallel by moving the receiver plate so that the contact pads couple to the probes.


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Littlebury, Hugh. (1991). Method for parallel testing of semiconductor devices (U.S. Patent No. 5012187). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5012187

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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