The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 1991

Filed:

Jul. 07, 1989
Applicant:
Inventor:

Pierre Jeuch, Seyssins, FR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 52 ; 437 40 ; 437 43 ; 437 48 ; 437 49 ; 437 61 ; 437 63 ; 437 64 ; 437190 ; 437191 ; 357 235 ; 357 231 ; 357 239 ;
Abstract

The invention concerns the method to produce an EPROM or EEPROM type integrated memory cell on a semiconductor substrate. The cell comprises memory points, electrically insulated from each other, each memory point comprising a source (4), a drain (6), a floating gate (350), a control grid (38), a channel (5) situated under the floating gate (350), the source (4) and the drain (6) being situated on both sides of the floating (350), the floating gates of each memory point being laterally distant and insulated along a first direction (X) from one or two other floating gates, the production of the cell comprising a stage for embodying lateral insulations (320) of the floating gates along the first direction (X), then a stage for embodying the actual floating gates (350), which makes it possible to obtain insulations between submicronic floating gates. Application for the embodiment of integrated memory cells.


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