The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 1991
Filed:
Sep. 07, 1990
Applicant:
Inventors:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364758 ; 364707 ;
Abstract
A parallel multiplier consists of a systolic array of AND gates and full adders organized in stages so that each stage generates a partial product, adds it to the preceding partial products, and furnishes the sum to the next stage. A control circuit is provided that disables the outputs of each stage of the array until the operation in the particular stage is completed. The disabling of outputs reduces power consumption.
Nishimura, Eiichi. (1991). Multiplying unit circuit (U.S. Patent No. 5010510). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5010510
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile