Spurious level reduction and control method for direct digital

Abstract

A direct digital synthesizer that outputs at least a predetermined output frequency related signal from a received digital signal, K, with minimum spurious signal levels. A storage device stores an initial phase value of the digital signal, K, and provides the initial phase value on an output thereof. An adder is provided having a first input for receiving the digital signal, K, having a second input and having an output which provides a summation of signals received on the first and second inputs. A latch has a first input connected to the output of the storage device, has a second input connected to the output of the adder and an output connected to the second input of the adder. The latch also has a third input for receiving a select signal for selecting between receiving on the first and second inputs of the latch. A control circuit provides the select signal in response to one of a plurality of predetermined parameters. The output frequency related signal is provided on the output of the latch. One or more detectors identify a power interrupt of the direct digital synthesizer or a change in the digital signal, K, and provides a detect signal to the control circuit. When a power interrupt or change in K is detected, the control circuit causes the latch to first receive the initial phase value on the first input thereof and then switch to the second input thereof for subsequent operations.