The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 1991
Filed:
Apr. 26, 1989
Kenji Matsumoto, Aiko, JP;
Tomoatsu Yanagita, Ebina, JP;
Yoshinori Nishiyama, Odawara, JP;
Masahiko Nagai, Naka, JP;
Mitsuru Morikuni, Ebina, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi Computer Engineering Co., Ltd., Kanagawa, JP;
Abstract
A load distribution method in which loads are divided into groups and each of a plurality of input pins of integrated circuits of a load is wired continuously with one stroke of a signal transmission line in a sequence from a driving output pin in each group when the wiring for distributing the drive signal from the driving output pin of an integrated circuit to plural input pins of integrated circuits, functioning as a load, is such that a plurality of intergrated circuits are mounted at given positions on a printed circuit board. In the load distribution method, the load is divided into groups by equally distributing a number of the loads so as to allow load capacities to be equal to each other on each of a plurality of signal transmission lines, and there is computed a signal propagation delay time of the signal transmission line wired equally in a distance to a load which is equal in a wiring sequence from the driving output pin in each group. Also, the loads are grouped by determining a combination of loads in which the signal propagation delay time of the signal transmission line becomes the shortest.