The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 1991
Filed:
Mar. 15, 1990
Shinichi Hisano, Boston, MA (US);
Apparajan Ganesan, Salem, NH (US);
Thomas S Guy, Andover, MA (US);
Analog Devices, Incorporated, Norwood, MA (US);
Abstract
A monolithic chip with an integrated circuit forming an 18-bit D/A converter powered by a single supply of .+-.5 volts. The circuit includes a voltage reference producing two stable voltages of 3.5V and 2.5V which are directed to a control amplifier. This amplifier produces control signals for the current-source cells of a current-steering network utilizing a segmentation decoder for the three most significant bits, a collector-connected R/2R ladder for the intermediate bits, and an emitter-connected R/2R ladder for the remaining least significant bits. The control signals include one for setting the level of current through an NPN current-source transistor, a second for setting the level of current through a PMOS transistor for turning on or off a pair of switching transistors, and a third for establishing a bias voltage for the turn-on circuits for the NPN current-source transistor. An output operational amplifier has its inverting input connected to the output of the current-steering network and to a bipolar offset current circuit powered by the 3.5V output of the voltage reference. The non-inverting input of the amplifier is connected to the 2.5 volt reference voltage to establish a pseudo-ground for the amplifier. A temperature-compensation circuit is provided for the emitter-connected R/2R ladder, and uses only NPN transistors without requiring any elements interfering with the operation of the current-source transistors, and without requiring an associated amplifier.