The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 1991

Filed:

Jun. 11, 1990
Applicant:
Inventors:

Roger D Norwood, Sugarland, TX (US);

David V Kersh, III, Houston, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
3074821 ; 307303 ; 3074651 ; 307475 ; 3072963 ;
Abstract

An input circuit for an integrated circuit furnishes a level shifting buffer portion adjacent a respective bond pad carried at the margin of the substrate while furnishing a clocked or latched portion adjacent the internal circuit of the integrated circuit. A lead extending from the level shifting or buffer portion to the clocked or latched portion carries the external signal applied to the bond pad and level shifted by the level shifting or buffer portion. The lead is subject to the parasitic resistance and capacitance of the integrated circuit. A multiplexer can be used to select among the level shifting portions for applying a single signal to the clocked portion and the clocked or latched portion can be part of a larger latch that receives plural signals for transmission to the internal circuit at appropriate times.


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