Dram with a vertical capacitor and transistor

Abstract

A dynamic random access memory array is formed using vertical transistors and capacitors. The capacitor for each memory cell has one electrode formed in a lower region of a pillar and a second electrode in a conductive fill surrounding the lower region of the pillar. The transistor of each cell has its source, drain, and channel also formed in a single pillar. The gate of each cell is a conductive layer surrounding the channel. The conductive layer is above and insulated from the conductive fill. The conductive layer is also conveniently the word line which continuously extends from one cell in a particular row to the next cell of that row. Contact to the cell is made to the top of the pillar which is doped to the same type as that of the lower region of the pillar. The areas between the pillars is filled with insulating material but the top of the pillar is exposed. Metal bit lines are thus conveniently formed in contact with the top of the pillar which is the input/output for the cell.