Self-aligned npn bipolar transistor built in a double polysilicon cmos

Abstract

The present invention provides a method, and a product made by the same, of fabricating an NPN bipolar transistor of a novel design simultaneously with the fabrication of double polysilicon CMOS/FAMOS devices, on an integrated circuit device. N wells 14 and 16 for the NPN transistor and the PMOS device are fabricated simultaneously. P type material is implanted to form the voltage adjust implant layer 19 of the FAMOS structure, and the base layer 18 of the NPN bipolar transistor, in the same process steps. In the process steps of forming the floating gate structure 36 of the FAMOS transistor, a polysilicon region 34 is also formed on the NPN transistor site. This polysilicon region 34 serves as a self-aligned implant mask during the implant of the base regions 88 of the NPN transistor. N type material is implanted in the same process steps to form the source and drain regions 66 of the FAMOS transistor and the emitter region 64 of the NPN transistor. N type material is implanted in the same process steps into the source and drain regions 86 of the NMOS transistor, and the collector regions 85 of the NPN transistor. P type material is implanted in the same process steps into the source and drain regions of the PMOS transistor 90, and into the base region 88 of the NPN transistor.