The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 1991
Filed:
Sep. 08, 1989
Asao Morikawa, Nagoya, JP;
Kazuo Kondo, Nagoya, JP;
NKG Spark Plug Co., Ltd., Tokyo, JP;
Abstract
A device for connecting a metal conductor on a surface of a first ceramic body to an outer terminal in which dispersion of copper metal into adjoining layers is prevented. An outer surface conductor made of Cu or Au is connected to the metal conductor on the surface of the ceramic body and extends through a throughhole in a second ceramic body. A lower conductive layer of Pd is formed over and in electrical connection with the outer end of the outer surface conductor, the lower layer having an area greater than the area of the outer end of the outer surface conductor. A dispersion-preventing layer is formed on a portion of the lower layer concentric with the outer end of the outer surface conductor, the dispersion-preventing layer having an area greater than the area of the outer end of the outer surface conductor but less than the area of the lower layer. The dispersion-preventing layer is made of a crystallized glass material. An upper conductive layer is formed over the dispersion-preventing layer and a portion of the lower layer, the upper conductive layer having an area greater than the area of the dispersion-preventing layer but less than the area of the lower layer. A soldering layer formed over the upper layer and a portion of the lower layer in electrical contact with the upper layer and the lower layer, the outer terminal being connected to the soldering layer.