The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 1991

Filed:

Aug. 15, 1990
Applicant:
Inventor:

Yasuo Naruke, Kawasaki, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; B01J / ;
U.S. Cl.
CPC ...
437 48 ; 437 49 ; 437 50 ; 437 52 ; 357 235 ; 357 236 ; 365103 ; 365104 ; 365185 ;
Abstract

A manufacturing method of a mask-ROM of two-layered gate electrode structure is provided. With this method, a cell transistor having a first-layered gate is converted into the depletion type according to data to be stored in the following manner. That is, a first conductive layer is insulatively formed over a semiconductor substrate of a first conductivity type, a silicon nitride film is formed on the first conductive layer, a polysilicon film is formed on the silicon nitride film, the polysilicon film is patterned and then altered into a silicon oxide film so as to increase its volume, and the silicon nitride film is patterned with the silicon oxide film used as a mask to form windows for permitting impurity to be doped therethrough. Then, impurity for converting cell transistors into the depletion type according to data to be stored is doped from the windows into the substrate through the first conductive layer.


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