Dac current source bias equalization topology

Abstract

A DAC includes a simple width-scaled weighted array (104) of N number of current sources and a weighted cascode current divider (108) comprised of m number of current sources. The simple width-scaled weighted array conducts N first scaled currents (I.sub.0 -I.sub.3), the array including N first transistors (116a-116d) connected to different ones of N second transistors (112a-112d), one of the N second transistors (112d) having a gate width w. The weighted cascode current divider includes M current sources, the current divider including M third transistors (120a-120d) that conduct M second scaled currents (I.sub.4 -I.sub.7) which are summed at a node (134). The node is connected to a master current transistor (138) that conducts a current I.sub.S and has a gate width w. In one embodiment, the bias of the N first transistors is tied to the node, whereby relative magnitudes of the N first scaled currents remain in correct proportion to relative magnitudes of the M second scaled currents in spite of changes in the magnitude of current I.sub.S. In another embodiment, the first and second inputs to an operational amplifier are connected to the node and the drain of the transistor of the second N transistors having a gate width w, respectively. The output to the operational amplifier is connected to the bias of the N first transistors. The DAC could have twelve bits with, for example, N=6 and M=6.