Fabrication of dielectrically isolated semiconductor device

Abstract

Improved dielectrically isolated semiconductor structures especially suited for very high frequency bipolar transistors are produced. Recesses are formed in a (e.g., N.sup.+) single crystal semiconductor wafer, the wafer surface is coated with a dielectric, and a thick polycrystalline semiconductor layer is deposited thereon to provide a support. The single crystal wafer is back-lapped to expose dielectrically isolated N.sup.+ islands located between the original recesses. Depressions are etched in the N.sup.+ islands and the exposed surface is covered by a more lightly doped (e.g., N.sup.-) semiconductor layer which is, generally, single crystal above the N.sup.+ islands and non-single crystal therebetween, and which at least fills the depressions. The structure is then planarized (e.g., by lapping and etching) to remove this non-single crystal material and give isolated single crystal islands having a surrounding N.sup.+ periphery and an N.sup.- central epi region of well controlled thickness and a smooth outer surface suitable for device formation. Bipolar transistors of excellent properties are formed by providing a nested base and emitter within the central region. Other types of devices may also be formed. The surrounding N.sup.+ periphery automatically provides a buried layer and buried layer contact.