The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 1991
Filed:
Mar. 07, 1989
Tomoji Nukiyama, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A full adder has a carry producing circuit responsive to at least two input bits and a low order carry bit and producing a carry bit, and a sum producing circuit responsive to the two input bits, the low order carry bit and the carry bit and producing a sum bit, wherein the sum producing circuit is provided with a first sum producing portion activated in the co-presence of the two input bits of logic '1' level or logic '0' level and the low order carry bit of logic '1' level or logic '0' level to produce the sum bit, and a second sum producing portion activated in the co-presence of at least one of the input bits and the low order carry bit different in logic level from the other bits to produce the sum bit opposite in logic level to the carry bit, so that signal propagation path is reduced in length, thereby achieving a high speed operation.