System with plural clocks for bidirectional information exchange between

Abstract

An interface mechanism is described for controlling the exchange of information between two devices, such as a direct memory access controller 12 and adapter 5 through bus 10. The exchange is initiated by the adapter which activates the request line 44 and read/write signal on line 62 indicating whether a memory read or write operation is requested. The controller sends back a grant signal on line 46 when the request may be serviced. Ready line 60 is monitored and checked by the adapter and valid line 52 is monitored and checked by the controller. Turn around signal on line 64 controls the direction of the transfer on bidirectional data lines 66. A write or read operation begins with the transmission by the adapter of control parameters (address and byte count). Then for a write operation, the data burst is sent from the adapter to the controller and for a read operation the data burst is sent from the controller to the adapter. The sampling clock always travels with the parameters and data. Controller 12 transmits data with a clock 28 used by the adapter to sample that data and adapter transmits data with a clock 36 used by the controller 12 to sample that data. Clock 36 is generated by inverting clock 28. Thus the bus presents the advantages of synchronous and asychronous modes of operation. The data exchanges are synchronous, so that no time is wasted in handshaking protocols. Because of its asynchronous nature between transfers, the bus is independent of the controller data handling scheme, memory type and memory access time.