The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 1991
Filed:
Oct. 27, 1988
Karel E Kuyk, Eindhoven, NL;
Jan W Slotboom, Eindhoven, NL;
Geert J Davids, Eindhoven, NL;
Wiegert Wiertsema, Eindhoven, NL;
Arie Slob, Eindhoven, NL;
U.S. Philips Corporation, New York, NY (US);
Abstract
A first charge storage electrode (21) has a first row (21b) of teeth interdigitated with a second row (22b) of teeth of a second charge storage electrode (22). The second storage electrode (22) has a third row (22c) of teeth interdigitated with a fourth row (23b) of teeth of a third charge storage electrode (23). The first and third rows (21b and 22c) overlie one group (11b) of a series of parallel conduction channels while the second and fourth rows (22b and 23b) overlie another group (11a) of the parallel channels. A first charge transfer electrode (24) is provided to transfer charge packets into sites beneath the first storage electrode. Second, third, fourth and fifth charge transfer electrodes (25, 26, 27 and 28) are provided to transfer charge packets between sites beneath, respectively, the first storage electrode (21) and the second row (22b), the first row (21b) and the second storage electrode (22), the second storage electrode (22) and the fourth row (23b), and the third row (22c) and the third storage electrode (23). The first, second and third storage and associated transfer electrodes may form an output stage (20) of a parallel register (C) of a series-parallel-series device to enable de-interlacing of rows of information.