Fabrication of cmos integrated devices with reduced gate length and

Abstract

By means of a single additional masking step lightly doped drain regions are formed in p-channel and n-channel CMOS transistors. The improved CMOS process comprises, after having formed the gates within the active areas and before forming spacers along the sides of the gate, implanting over the entire unmasked surface of the front of the device formed on a silicon substrate of a first polarity a quantity of dopant of a second polarity, identical to the well region polarity, sufficient to form lightly doped drain regions in transistors with a channel of said second polarity, forming a first time the mask for implantations of said first polarity and implanting the relative dopant in a dose sufficient to compensate and invert completely the previous implantation and to form lightly doped drain regions in transistors with a channel of said first polarity formed within the well region. The fabrication process may then continue in a conventional way.