The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 1991
Filed:
Jan. 12, 1990
John R Stice, Redmond, WA (US);
Physio-Control Corporation, Redmond, WA (US);
Abstract
A differential lead impedance comparison apparatus (10) senses lead impedance and compensates for patient-to-patient and electrode variability. A bridge circuit (12) is connected to one end of electrode conductors (22, 24 and 26) in an ECG Leads I configuration. The other end of the conductors (22, 24 and 26) are connected to a patient (18) via electrodes (RA, LA and LL). Leads formed in part by RA, LA and LL and the respective conductors (22, 24 and 26) have lead impedances (R.sub.b, R.sub.a, and R.sub.c). Constant current sources (11, 12 and 13) are connected to the conductors (22, 24 and 26) and supply constant AC currents (I.sub.1, I.sub.2 and I.sub.3). A first bridge output voltage (V.sub.M) is produced by I.sub.1 and a combination 32 of R.sub.a, R.sub.b, and R.sub.c. A second bridge output voltage (V.sub.P) is produced by I.sub.2 and a combination 34 of R.sub.a, R.sub.b, and R.sub.c. A differential amplifier circuit (14) differentially amplifies the V.sub.M and V.sub.P voltages to produce differential voltages (V.sub.OM and V.sub.OP). Demodulators (DM1 and DM2) demodulate V.sub.OM and V.sub.OP to produce differential impedance voltages (V.sub.1M and V.sub.1P). A first comparator (OA3) changes states and produces a high logic output when V.sub.1M equals or exceeds a first threshold level (V.sub.TH1). A second comparator (OA4) changes states and produces a high logic output when V.sub.1P equals or exceeds a second threshold level (V.sub.TH2). An exclusive OR gate (G1) produces a high logic output (V.sub.OUT) when one and only one of OA3 or OA4 produce a high logic output.