High speed memory cell with multiple port capability

Abstract

A semiconductor memory cell for selectively storing or outputting differential signals responsive to a SELECT signal supplied on a word line includes: a transistor pair having cross-coupled base-collector terminals and emitter terminals connected to a common reference potential; a sensing circuit connected to each of the base-collector terminals in the transistor pair, each of the sensing circuits including (a) a first diode having a cathode connected to the base-collector terminal, (b) a second diode having an anode connected to the anode of the first diode and a cathode connected to the word line, and (c) a circuit connected at the commonly connected anodes of the first and second diodes for amplifying the signal thereat; a writing circuit connected to each of the transistors in the transistor pair, the writing circuit including a transistor having a base connected to the word line and a collector connected to the base-collector terminal; and a circuit for supplying constant current to each of the base-collector terminals and to each of the commonly connected anodes of the first and second diodes. The memory cell permits read access or select while maintaining the voltages on the latch nodes stable.