Serial clock generating circuit

Abstract

A serial clock generating circuit for generating a serial clock in phase with a clock included in a received serial data on the basis of an input clock having a frequency N times of a serial data transfer rate of the received serial data, comprises an edge detector for detecting a level transition of the received serial data so as to generate a level transition detection signal, and a counter for counting the input clock. A first comparison register is provided for comparing a count value of the counter with a first programmable predetermined value at each one counting operation of the counter, so as to generate a first coincidence signal when the count value of the counter is coincident with the first programmable predetermined value. A second comparison register is provided for comparing the count value of the counter with a second programmable predetermined value at each one counting operation of the counter, so as to generate a second coincidence signal when the count value of the counter is coincident with the second programmable predetermined value. A capture/comparison register operates to capture and store the count value of the counter when the level transition detection signal is generated, and also to compare the count value of the counter with the stored count value at each one counting operation of the counter, so as to generate a third coincidence signal when the count value of the counter is coincident with the stored count value. There is provided a clear circuit for generating a clear signal to the counter when either the first coincidence signal or the third coincidence signal is generated. A serial clock generator generates a serial clock signal on the basis of the second coincidence signal and the clear signal.