Phase locked loop circuit with digital control

Abstract

A Phase Locked Loop (PLL) circuit includes a control signal generator, a digital phase detector, logic gates, a charge pump (charge/discharge circuit), a transmission gate, a loop filter, a lead-lag filter and a voltage controlled oscillator (VCO). Outputs of the digital phase detector are coupled through the logic gates to inputs of the charge pump. An output of the charge pump is coupled to the capacitor and to a first input/output of the transmission gate. A second input/output of the transmission gate is coupled to an input of the loop filter whose output is coupled to an input of the VCO whose output is coupled to a first input of the digital phase detector. A second input of the digital phase detector is coupled to a source of a reference frequency signal. The control signal generator generates non-overlapping complementary control signals with one of same connected to the logic gates and the other connected to the transmission gate. Accordingly, the electrical path from the digital phase detector to the charge pump through the logic gates is closed and the electrical path from the capacitor to the loop filter is open or vice versa. The loop filter includes an operational amplifier with AC feedback which is controlled by the same signal which controls the logic gates. The PLL circuit is typically formed on a single integrated circuit silicon chip using CMOS technology.