Monolithic phase-locked loop

Abstract

A phase-locked loop (PLL) circuit, manufacturable using standard integrated circuit technology, includes a sampled-data phase detector, a sampled-data loop filter for filtering the output of the phase detetector, a voltage controlled oscillator driven by the output of the loop filter, and a frequency divider in the feedback loop. A clock circuit generates reference signals needed by the other circuit components. The sampled-data phase detector, under the control of two clocks of differing frequencies, derives a phase error signal through the use of discrete-time analog integration of its input signal. When the PLL is in lock, this phase detector outputs valid phase error signal at discrete time intervals. The gain of the phase detector is proportional to a ratio of capacitor values, a ratio of frequencies, and a reference voltage, all of which can be made substantially independent of variations in temperature and semiconductor processing. A separate frequency acquisition circuit is used to prevent false locking of the PLL on an erroneous frequency. The outputs of this frequency acquisition circuit are fed to the loop filter by a switched-capacitor circuit arrangement that automatically removes the frequency acquisition circuit from the feedback loop once frequency acquisition has been achieved. The sampled-data loop filter emulates the response of continuous-time filters by replacing resistors with switched capacitors. The loop filter response is, to first order, a function only of capacitor ratios and the frequency of a reference clock.