The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 22, 1991
Filed:
May. 30, 1989
Applicant:
Inventors:
Virgilio A Fernandez, Sunrise, FL (US);
Gianfranco Gerosa, Austin, TX (US);
Assignee:
Motorola, Inc., Schaumburg, IL (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06G / ; H03K / ;
U.S. Cl.
CPC ...
307491 ; 307494 ; 3072964 ; 3072965 ;
Abstract
A CMOS differential amplifier or comparator circuit (100) is provided having minimized DC offset voltage. The circuit includes parallel coupled stages (110, 120, 130, 140, 150, 160) that are selectively controlled by an F.E.T. switch (182). The current through each stage is a function of its FET sizing. The current through the differential amplifier is adjusted by the selectively activated certain stages, which increase the current through differential amplifier (100), thereby adjusting the DC offset. The FETs in each stage are sized differently to allow flexibility in adjusting DC offset voltage.