The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 15, 1991

Filed:

Oct. 25, 1988
Applicant:
Inventors:

Hiroyuki Mano, Yokohama, JP;

Terumi Takashi, Yokohama, JP;

Kazuhiro Fujisawa, Fujisawa, JP;

Kaoru Hasegawa, Chiba, JP;

Shinzo Matsumoto, Mobara, JP;

Mitsuhisa Fujita, Chiba, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G / ;
U.S. Cl.
CPC ...
340784 ; 340805 ;
Abstract

An apparatus for driving a color display panel operating at a high frame frequency. The color display panel driving apparatus includes a line memory for storing data of 1/2 of a line at its odd-numbered addresses and then storing data of the remaining 1/2 of the line at its even-numbered addresses, a first column drive circuit including a shift register to which the data stored at the odd-numbered addresses of the line memory are supplied and which is connected at its bit outputs to column-direction signal wires associated with a left-hand half display area of the display panel, and a second column drive circuit including a shift register to which the data stored at the even-numbered addresses of the line memory are supplied and which is connected at its bit outputs to column-direction signal wires associated with a right-hand half display area of the display panel. After picture data of one line are completely stored in the line memory, the picture data are substantially simultaneously supplied from the odd-numbered and even-numbered addresses of the line memory to the first and second column drive circuits respectively.


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