The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 1991
Filed:
Nov. 22, 1988
Yoshihiko Okihara, Hyogo, JP;
Yutaka Arita, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
An output buffer circuit comprises a NAND circuit and a NOR circuit each receiving an output a of a signal source and an output b of an output control circuit and an output driving circuit formed by a p channel MOS transistor and an n channel MOS transistor receiving outputs of the NAND circuit and the NOR circuit. Large output capacitance is connected to an output of the output driving circuit. The n channel MOS transistor is connected between the output of the NOR circuit and a ground potential, and has its gate receiving the output of the output driving circuit. When the output of the output driving circuit is at an 'H' level, the rise of the output of the NOR circuit is controlled, so that the output of the output driving circuit is first changed to the 'L' level slowly. Therefore, discharge current from the output capacitance rises slowly. However, since transconductance of the n channel MOS transistor in the output driving circuit is set large, the output of the output driving circuit falls rapidly from halfway.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile