The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 1991

Filed:

Dec. 05, 1989
Applicant:
Inventors:

Nathan R Hiltebeitel, South Burlington, VT (US);

Robert Tamlyn, Jericho, VT (US);

Steven W Tomashot, Jericho, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ;
U.S. Cl.
CPC ...
36523005 ; 36523002 ;
Abstract

A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.


Find Patent Forward Citations

Hiltebeitel, Nathan. (1991). Multiplexed serial register architecture for vram (U.S. Patent No. 4984214). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4984214

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…