Non-linear analog-to-digital converter

Abstract

A first film disposed in a first direction on an integrated circuit chip and having uniformly spaced taps provides progressively increasing resistance values. A second film disposed on the chip in a direction opposite to the first direction at a position displaced in any direction from the first film may have a construction corresponding to that of the first film. First and second reference voltages may be respectively applied to the first and second ends of the first and second films. Particular taps on the first film may be connected to taps in corresponding positions on the second film with corresponding voltages. A plurality of differential comparators are provided, each with a signal input and a reference input. Each comparator reference input is connected to an individual one of the taps on the first film, but not necessarily to successive taps. The reference input connections to the taps may have a non-linear (e.g. a luminance) spacing in the first direction to provide a non-linear voltage (e.g. a luminance) relationship between such taps. For low voltages, however, the reference input connections to the taps may have a linear spacing in the first direction to provide a linear voltage relationship between such taps. An input voltage is applied to the signal input of all the comparators. Binary signals representative of the input voltage are produced by the comparator in which the input voltage is substantially equal to the reference input voltage introduced to such comparator.