Semiconductor integrated circuit with an input buffer circuit for

Abstract

A semiconductor integrated circuit comprises a first input circuit for generating an internal chip enable signal in response to a chip enable signal externally applied; and a second input circuit for supplying to an internal circuit a signal corresponding to a data signal externally applied thereto, the second input circuit containing a gate circuit controlled by an internal chip enable signal. The gate circuit responds to the data signal at a first response speed, and responds to the internal chip enable signal at a second response speed when the semiconductor integrated circuit is changed from the active state to the stand-by state. The second response speed being slower than the first response speed, so as to prevent the semi-conductor integrated circuit from being set into the stand-by state by a false operation of the first input circuit.