The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 1991

Filed:

Feb. 07, 1990
Applicant:
Inventors:

Takayuki Ohtani, Tokyo, JP;

Mitsuo Isobe, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518911 ; 365154 ; 365202 ;
Abstract

During a data-clearing operation, while maintaining in the OFF state the transfer gate transistors in each of the static type memory cells associated with at least one column, the source of one of two drive transistors incorporated in the memory cell is set to a high potential level, and the source of the other drive transistor to a low level. As a result, the clearing operation is performed to a minimum of 1 column in the memory cell matrix. Due to the arrangement of the memory device, no address-selecting operation is required for selecting a memory cell during the clearing operation. Moreover, the clearing operation is carried out in a minimum unit of 1 column in the memory cell matrix. Consequently, the processing time for the clearing operation is reduced. Furthermore, the DC current flowing during the clearing operation is reduced, since the transfer gate transistor in the memory cell is maintained in the OFF state during the clearing operation, with the result that the power consumption is lowered.


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