Logic signals generating and sequencing circuit for charge transfer

Abstract

This circuit is essentially formed by a circuit of the programmable (preferably reprogrammable) logic component type, receiving, at input, a reference clock signal (CK) and configured in such a way as to deliver, at output, the plurality of clock signals (.phi.1 . . . .phi.N) needed to control the charge transfer device. It is, notably, a programmable logic circuit configured so as to include, around a common general bus: first synchronized signals generating means receiving, at input, said clock signal, and applying, at output, to the general bus, a sequence of first binary configurations representing the horizontal sequencing of the charge transfer device; second synchronized signals generating means receiving, at input, a signal corresponding to the appearance of a particular binary configuration among said first binary configurations, and applying, at output, to the general bus, a sequence of second binary configurations, representing the vertical sequencing of the charge transfer device, and a plurality of sequencing means placed in parallel on the general bus, said sequencing means receiving, at input, the signals present at the general bus, and decoding these signals so as to respectively generate, at a given instant which is a function of said binary configurations and of said clock signal, one of said control logic signals.