The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 1990
Filed:
Jan. 13, 1989
Hikaru Hida, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
An atomic planar-doped field-effect transistor is disclosed, which is featured by a channel region of a limited thickness between source and drain with at least one atomic planar-doped layer formed therein and a barrier layer or layers provided on the upper or lower side or on the both sides of the channel region. The channel region is formed of a semiconductor of a low impurity concentration or of an n-type with the atomic planar-doped layer having high concentration donor impurities or of a p-type with the atomic planar-doped layer having high concentration acceptor impurities. The upper barrier layer is provided between the channel region and a gate electrode and the lower barrier layer, if present, is provided between the channel region and a substrate. They are formed of a semiconductor of a low impurity concentration which is different from the semiconductor of the channel region and makes a heterojunction with the channel region and which has a smaller electron affinity than the semiconductor of the channel region having the donor planar-doped layer or a larger value of a sum of electron affinity and energy gap than the semiconductor of the channel region having the acceptor planar-doped layer. With the upper barrier layer, the transistor of the present invention has a large gate-forward turn-on voltage. The short channel effects are suppressed by adding the lower barrier layer to the transistor.