The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 18, 1990
Filed:
Jul. 19, 1989
Ming-Daw Chen, Hsin Chu, TW;
Nang-Ping Tu, Hsin Chu, TW;
Abstract
The apparatus of the present invention is a CMOS digital level shifter circuit which includes an inverter connected to a voltage generator. The voltage generator comprises an NMOS source follower connected to a directional switching element and a voltage regulating capacitor. The level shifter further includes a latch energized by the same voltage supply energizing the voltage generator. Each branch of the latch has a complementary MOS transistor pair with common gates connected to the output of the inverter and to the input signal respectively. Each complementary transistor pair is connected to the voltage supply by a latch transistor whose gate is cross-connected to the complementary transistor pair of the other branch. Whenever the one transistor in each complementary pair which is connected to ground is on, the latch transistor is latched off by the complementary transistor pair in the other branch after each voltage transition by the input signal, thereby reducing or eliminating DC power consumption, while requiring only a single voltage supply.