The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 1990

Filed:

Jan. 27, 1989
Applicant:
Inventors:

Makoto Shiomi, Yokohama, JP;

Michitaka Ohsawa, Fujisawa, JP;

Toshiyuki Sakamoto, Fujisawa, JP;

Kuninori Matsumi, Fujisawa, JP;

Kosuke Ozeki, Yokohama, JP;

Ikuo Yuki, Yokohama, JP;

Kenji Sato, Yokohama, JP;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N / ;
U.S. Cl.
CPC ...
358 60 ; 358 64 ; 315368 ;
Abstract

A convergence correcting apparatus is used in a projection television receiver including a CRT having an aspherical fluorescent screen and a projection lens apparatus which is attached to the display screen of the CRT and has aspherical plastic lenses. In the digital convergence correcting apparatus, a digital memory stores digital correction data corresponding to correction values of convergence adjustments points indicative of a plurality of points on the display screens divided in the horizontal and vertical directions. A multiplexer reads out predetermined digital correction data from the digital memory and time sharingly multiplexes. At least one digital/analog converter receives the time sharingly multiplexed data from the multiplexer and generates an analog signal. Sample and hold circuits extract a predetermined correction signal from the analog output of the digital/analog converter and sample and hold them. The convergence correcting apparatus is driven in accordance with the respective correction signals held by the sample and hold circuits.


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