The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 1990

Filed:

Jan. 30, 1989
Applicant:
Inventor:

Akira Denda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307475 ; 307362 ; 307264 ; 307448 ;
Abstract

A semiconductor integrated circuit comprises a positive voltage line, a negative voltage line, a ground line, a first circuit connected between the ground line and one of the positive voltage line and the negative voltage line so as to be driven by a voltage difference between the ground line and the one of the positive voltage line and the negative voltage line, and a second circuit connected between the ground line and the other of the positive voltage line and the negative voltage line so as to be driven by a voltage difference between the ground line and the other of the positive voltage line and the negative voltage line. A signal level conversion circuit includes a MOS transistor having a gate connected to an output of the first circuit and a drain connected through a resistor to the ground line. A source of the transistor is connected to the other of the positive voltage line and the negative voltage line, and the drain of the transistor is connected to an input of the second circuit. This transistor has its threshold voltage whose absolute value is larger than an absolute value of a voltage difference between the ground line and the other of the positive voltage line and the negative voltage line.


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